Interfacing ROM with the CPU
The following figure shows how ROM or Flash chip is connected to the
CPU's bus lines. Note that Flash is a kind of ROM used extensively now a days.
Basically both are non-volatile memory chips. Every chip that is connected to
the CPU, will have Address pins, data pins and control pins. Control pins
are read and write pins. The number of address pins of a memory chip,
depends on the size of memory. If memory has got 1 K(1024) locations,
then it will have 10 address lines. This is because 2 power 10 is 1024.
Every chip also will have one important pin called 'Chip Select' or CS for
short. This pin is not shown in the figure. The CS pins of all the chips are
connected to one address decoder chip. This address decoder chip (not shown
in the figure) takes most significant address lines from the CPU as input
and generates individual chip selects lines to each chip.
When CPU places the address on the address lines, based on the address,
decoder chip will activate only one chip select line. So for this address
only that chip will get selected. Now this chip will be active and participates
in the bus cycle. All other chips present on the bus, will not be active as
their chip select pin is not selected. In this way, even though multiple
chips are connected to the CPU's bus, only one chip will get selected for any
In the figure above, the ROM/flash chip has got 128 bytes of memory. So it
will have 7 address lines. CPU's address lines A0 to A6 are connected to these
7 address pins of the memory chip. When CPU places address in the range of
0 to 0x7F, the decoder will activate the chip select pin of this chip.
The eight data pins of memory chip are connected to the 8 data lines of the
CPU's bus. The read and write pins of memory chip are connected to the
read line and write line of the bus respectively. For a ROM chip, write line
may not be present. Flash is normally considered as read only memory, however
it also supports write in some special way. But for our purpose, we always
treat Flash as read only memory.
When CPU wishes to perform instruction fetch or memory read cycle, it
palces the address on the address bus. Because of this address, memory
chip will get selected through the address decoder. Once chip is selected
the address pins of the chip will select the individual memory location
on the chip. If address on the address pins A0 to A6 is 0x24, then 0x24th
(36th) location will be selected. While placing the address on the address
line, CPU also actives the read control line. This read control line, will
inform the seleced chip, that CPU wish to read the contents of the selected
memory location. On seeing read pin going active, the memory chip will place
the contents of selected location (here 36th location) on the data pins.
As these data pins of memory chip are connected to the, CPU's bus lines, the
data will reach to the CPU. CPU will read whatever data is present on the
Answer the following questions to check the understanding of the subject
1. What is the size of ROM/Flash chip interfaced to the CPU ? How many address
pins should be present for this ROM/Flash chip?
2. What is the purpose of read pin and write pin present in CPU and
3. Explain the purpose of 'Chip Select' pin present on the ROM chip